The present invention relates to a nonvolatile semiconductor storage device, and more particularly, to a method and an apparatus for rapidly and accurately trimming the values stored by reference cells used for reading a memory cell array of a nonvolatile semiconductor storage device.
Generally, reference cells are used for fast reading together with a plurality of memory cells arranged in a memory cell array of a nonvolatile semiconductor storage device. Specifically, each memory cell stores a certain value to output a voltage corresponding to the certain value. Each output voltage is compared with a predetermined threshold level given by each of the reference cells to decide a logical value of each output voltage.
In order to avoid changing a difference of characteristics between a cell transistor of each memory cell and a reference cell transistor of a reference cell, it is preferable that the reference cell transistor for each reference cell has a characteristic identical with the memory cell transistor. When both the reference and the memory cells are identical with each other in characteristic, the threshold voltage of each reference cell usually corresponds to a voltage of the memory cells given when the transistors of the memory cells are turned on.
In a rewritable nonvolatile storage, such as a flash memory, the threshold voltage of the reference cell is not always kept at a desired level immediately after a diffusion process into a wafer. To set the threshold voltage of the reference cell at the desired level, several methods have been proposed.
By way of example, consideration might be made like in a UVPROM (ultraviolet erasable programmable read-only memory) about a method of irradiating ultraviolet rays onto both the memory and the reference cells to set the threshold voltage of each reference cell to a desired value.
However, the above method has the following disadvantages. Namely, it needs a step of irradiating ultraviolet rays, in spite of the fact that such a step is unnecessary for manufacturing a flash memory essentially. In addition, each cell device must be designed so that the threshold voltage of the reference cell is kept at the desired level after irradiation of the ultraviolet rays. Further, layers over a wiring layer must be structured so that ultraviolet rays can arrive at a reference cell portion.
In order to avoid those disadvantages, trimming operation of a threshold voltage of a reference cell is carried out by electrically erasing and programming. In this event, the threshold voltage of each reference cell should be monitored by using a routine, like a routine for automatically writing in a memory cell and a routine for automatic erasing.
Such a method and an apparatus for monitoring the threshold voltage of each reference cell are disclosed by Bauer et al in U.S. Pat. No. 5,444,656.
In FIG. 1, the apparatus mentioned in the above-mentioned patent is illustrated which has a memory cell array 103, a column switch 104, a current-to-voltage converter 240 of a sense amplifier, and a reference circuit 106.
More specifically, the memory cell array 103 has transistors 212 which are arranged in rows and columns. In FIG. 1, each of reference symbols WL0 to WLm shows a word line while each of reference symbols BL0 to BLm shows a bit line.
The illustrated column switch 104 is formed by transistors 210 which are driven by control signals YS0 and YSn.
The current-to-voltage converter circuit 240 of the sense amplifier is connected to the column switch 104 through a node DIGi and is formed by load transistor 202, 203 and an inverter 204. The circuit 240 converts a discharge current passing through the node DIGi to a voltage.
The reference circuit 106 has reference cells 231, transistors 230 which are driven by control signals YS0, YSR1 and YSR2, and a current-to-voltage converter circuit 241 which is formed by a load transistor 205, 206, and an inverter 207.
A reference voltage VREF which is sent from the reference circuit 106 is furnished to one input terminal of a differential amplifier 201. The amplifier 201 has another input terminal given a voltage VSA generated in a manner to be mentioned hereinafter.
An additional circuit is arranged between the amplifier 201 and the current-to-voltage converter circuit 240 of the sense amplifier. The additional circuit has transistors 404 driven by a controller 403, pads 401 externally connected to testing circuitry and connected directly to another input terminal of the amplifier 201, a digital-to-analog converter circuit 402, and a switch 405.
In the prior art illustrated in FIG. 1, the pads 401 are arranged to furnish the voltage VSA from a test probe or the like during trimming operation carried out in a manufacturing process. The voltage VSA is compared to the voltage VREF given from the reference circuit 106 by the amplifier 201 and a threshold value of the reference cell 231 is evaluated from the difference between the voltages VSA and VREF.
With this structure, however, the pads 401 must be arranged as external terminals in order to verify the threshold voltage of the reference cell 231. Moreover, one input terminal of the amplifier 201 is directly given the voltage VSA during the trimming operation on the side of the memory cell array 103 while another input terminal is connected through the current-to-voltage converter circuit 241 to the reference circuit 106. Consequently, the illustrated circuit is liable to be adversely affected by a variation caused to occur during a manufacturing process of the current-to-voltage converter circuit 241. Accordingly, precise control can not be realized.